What is a Chiplet, and Why Has Packaging Become the Real Chokepoint in Chipmaking?
For six decades, semiconductor progress meant one thing: shrinking transistors. That logic still holds for raw compute density — but it no longer describes what separates the chips that ship from the chips that don't. In 2026, the real chokepoint in AI silicon is not the lithography machine. It is the package.
What a chiplet is. A chiplet is a small, modular die designed to connect to other dies within a single package rather than function as a standalone chip. Instead of manufacturing one enormous monolithic die containing every processor function — compute cores, memory controllers, I/O interfaces, accelerators — engineers divide that functionality across several smaller dies, each optimised for its task and fabricated on whichever process node makes economic sense.
The yield logic is what drives adoption. The proportion of working dies on a wafer falls exponentially as die area grows. A monolithic flagship GPU approaching 600mm² on a leading node achieves 50–55% yield; a 100mm² chiplet consistently achieves 90% or better. Every failed die on a $20,000 wafer is wasted cost. Chiplets restructure that equation — at the price of a new engineering challenge: connecting them fast enough to behave as a single unified chip.
Who pioneered it and where it stands. AMD launched the modern chiplet era with its Zen architecture in 2017, separating CPU compute dies from the I/O die and manufacturing each on its optimal node. NVIDIA's Rubin and Intel's Granite Rapids follow the same discipline. Apple's M-series achieves related goals through tight memory-logic co-packaging rather than discrete chiplet interconnects — a distinction that underlines chiplets as an economic strategy, not a single rigid architecture.
What every chiplet design shares is the package. The package must carry data between dies at bandwidths that would have required on-chip wiring a generation ago. A modern AI accelerator demands terabytes per second of die-to-die interconnect. That demand has spawned an entirely new tier of semiconductor infrastructure — and exposed the industry's newest single point of failure.
Chiplet yield advantage: why smaller dies dominate leading-edge economics
Illustrative yield curve using Poisson model (D = 0.1 defects/cm²); annotated with real-world die examples
Source: Poisson yield model (Y = e⁻⁽DA⁾, D = 0.1 defects/cm²) — standard industry approximation. Real-world yield varies by node, design, and fab. H100 die area from public NVIDIA/TSMC disclosures. ATF illustration.
Chiplet economics: lower die cost offsets higher packaging cost — with room to spare
Illustrative cost breakdown per unit, USD; hypothetical 600mm² equivalent compute at leading node
Source: Illustrative model based on SemiAnalysis yield-cost framework; TSMC advanced node wafer pricing (industry estimates); McKinsey semiconductor cost model (2024). Numbers are illustrative — actual cost varies by design, volume, and vendor agreement.
“The question that determines whether an AI accelerator ships on schedule is not ‘can you print at 2nm?’ It is ‘can you get a CoWoS slot?’”
Colin Tan, Editor — Asia Tech Feed
Why CoWoS became the bottleneck. TSMC's CoWoS — Chip on Wafer on Substrate — sits at the centre of the AI supply chain. In CoWoS-S, chiplets are mounted on a silicon interposer providing thousands of microbumps at pitches as fine as 40μm; in CoWoS-L, the interposer is extended with a localised silicon bridge. The result is die-to-die bandwidth measured in terabytes per second — versus the gigabytes a PCB trace can manage.
The constraint is capacity, not technology. CoWoS output more than doubled in 2025 to roughly 70,000 wafers per month and is on track to double again by end-2026 to approximately 140,000. It is still not enough. NVIDIA has reportedly secured over 60% of TSMC's 2026 CoWoS allocation for the Rubin ramp alone. The package slot, not the silicon wafer, is what limits how many AI accelerators ship this year.
The geography of packaging. The advanced packaging map is overwhelmingly Asian. TSMC dominates with CoWoS and its 3D stacking platform SoIC. ASE Group — the world's largest OSAT — operates primarily in Taiwan and Malaysia. Amkor's Korean and Malaysian facilities, JCET in China, and Unimicron's ABF substrate plants all sit within this region.
Japan is co-locating packaging with wafer production at Rapidus' Chitose campus. Malaysia's Penang corridor absorbs OSAT overflow as supply chains de-risk from Taiwan concentration. India's semiconductor ambitions are explicitly packaging-first: the Tata Electronics and CG Power OSAT projects target assembly and test, not wafer fabrication. The logic is straightforward — advanced packaging does not require EUV lithography, so entry barriers are lower even as strategic value rises rapidly.
Supply doubles twice — and still chases demand every year through 2027
CoWoS-equivalent advanced packaging capacity (supply, bars) vs estimated AI accelerator demand (line), thousand wafers per month
Source: TrendForce; Focus Taiwan / TSMC Technology Symposium (2026); Commercial Times; Tom's Hardware. Demand line is ATF estimate derived from hyperscaler GPU order disclosures and CoWoS wafer intensity ratios. 2026–27 are forecasts.
What comes next: CoPoS and the panel revolution. Two technologies define the next inflection. CoPoS — chip on panel on substrate — scales CoWoS from a 300mm round wafer to a rectangular panel, cutting per-unit packaging cost by an estimated 40–60%. A single Rubin-scale package today occupies most of a 300mm wafer; panel-level packaging changes that arithmetic fundamentally. TSMC has a pilot line running with volume production targeted for 2028–29. The transition would represent the most significant reduction in AI accelerator packaging cost since CoWoS itself was introduced.
3D stacking and the shift of gravity. The second frontier is 3D stacking. TSMC's SoIC bonds dies face-to-face using hybrid bonding — copper-to-copper connections at 9μm pitch with no solder bump — enabling memory-to-logic bandwidth no interposer can match. Intel's Foveros Direct achieves similar densities. When 3D packaging matures at volume scale, estimated around 2028–30, the centre of gravity in chipmaking shifts further from the wafer fab toward the package house. The era of packaging as an afterthought — a low-margin service attached to real semiconductor work — is definitively over.
The transistor count on a chip still matters. But in 2026, the question that determines whether an AI accelerator ships on schedule — and at what cost — is not "can you print at 2nm?" It is "can you get a CoWoS slot?" Packaging has become the most strategically valuable, most supply-constrained, and most geographically concentrated step in modern chipmaking. Any organisation buying, building, or pricing around AI infrastructure should understand it with the same rigour as the silicon itself.